ECE 2020 Digital Design

Prof. Matthieu Bloch

Wednesday, September 24, 2025 (v1.0) - Gates

Last time

  • Last time
    • CMOS logic: use nMOS and pMOS to create ideal switch
    • Composite switch required to go around non-ideal behavior
    • Pull Up Networks and Pull Down Networks
  • To be effectively prepared for today you should have:
    • Read your notes
  • Important notes
    • Homework 3 assigned on Wednesday September 24, 2025 (today)
    • Breanna's office hours Thursdays 2-3pm in TSRB 530
    • Dr. Bloch office hours Wednesday 8:30am-9:30am
    • Lab next week! Information released today after we cover required concepts
      • There is a pre-lab
  • Today
    • We will continue talking about the implementation of boolean functions using CMOS logic
  • Be ready!
    • I expect you to take notes
    • We will take a quizz on canvas for attendance

Last Time: CMOS Logic

  • Step 1: separate the variables using DeMorgan's law as needed
  • Step 2: draw the Pull Up Network (PUN)
    • OR: pMos in parallel
    • AND: pMOS in series
    • connect gates to inverse of variables
  • Step 3: draw the Pull Down Network (PDN) for the dual function
    • OR: nMOS in parallel
    • AND: nMOS in series
    • connect gates to inverse of variables

Example: NAND

Example: NOR

Example: more complicated boolean expression

  • Example 1: \(D=A\cdot\overline{C}+B\)

  • Example 2: \(F = E\cdot(\overline{A}\cdot D+\overline{B}\cdot(A+\overline{C}))\)

Gate design

  • How do we scale up a design
    • Instead of going back to CMOS logic every time, we will design basic gates
    • This will allow us to use modular design to implement complext functions
  • General approach
    • Only one connection per input (either Vcc or GND or output of other gate)
    • Output can drive input or other gate
  • Learn how to recognize valid and invalid networks!

A zoo of gates

Implementing Boolean functions

  • Simply replace the logical operators by their corresponding gates
    • Very natural to do with AND, OR, NOT
  • What if we require a specific set of logic gates (say NAND)?

Mixed logic

  • Mixed logic is a gate design methodology
    • separate functional description from physical implementation
    • implementation should not prevent you from figuring out what the circuit does

Until next time

  • To be effectively prepared for Monday September 29, 2025, you should:
    • Read your notes and review the examples
    • Start working on Homework 3
    • Start working on your pre-lab